Understand the Problem (Discovery)​

Define why this device is being built and what conditions it must endure before selecting materials or stackups.

Start by asking:

• What is the function of the device? (e.g., RF filter, sensor, implant)

• What is the operating frequency range?

• What are the key electrical requirements—impedance, signal integrity, Q-factor?

• What’s the thermal profile—power dissipation, ambient environment?

• Is the device rigid, flexible, or semi-flex?

• What kind of environment will it operate in—vacuum, body fluids, reflow soldering, radiation?

• Are there any size or mechanical constraints—thickness, footprint, board size?

• What compliance or standards must it meet—MIL-STD, ISO 13485, RoHS, NASA?

This step aligns your design goals with practical build choices and constraints—so decisions around materials, processes, and layout are anchored in real-world needs.

Example: If you're building a microwave filter for a satellite:

• Electrical: Operates at 18–26 GHz with return loss < -15 dB

• Thermal: Must withstand -40 to +85°C, low outgassing

• Mechanical: Vibration during launch; low mass

• Compliance: MIL-spec, radiation tolerance

• Materials (determined later): Likely quartz, with filled vias and gold top metal

Substrate Selection for High-Performance Thin-Film Circuits

Where precision materials meet signal integrity, thermal performance, and reliability.

Why Substrate Choice Matters

In high-frequency and mission-critical environments, your substrate isn't just a base—it's the backbone. It governs everything from signal integrity to thermal dissipation and long-term yield. Start here.

Substrate selection drives:

• Dielectric behavior – Controls impedance, losses, and frequency response.

• Thermal handling – Impacts power density, heat spread, and failure rate.

• Mechanical integrity – Influences yield, handling damage, and packaging.

• Surface quality – Affects pattern resolution, metal adhesion, and process control.

• Process compatibility – Determines etch performance, coating uniformity, and chemical resilience.

• Lead time and cost – Premium substrates bring performance—but also logistics challenges.

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Practical Design Guidelines

Substrate: (Typical Thickness - 125 µm (5 mil) to 500 µm (20 mil))
Thinner substrates offer better RF performance but may compromise handling. Choose based on application stress, packaging demands, and frequency targets.

Edge Clearance: Maintain at least 75 µm (3 mil) between active features and substrate edges.
This reduces risk of damage during dicing, singulation, or assembly.

Surface Finish: Polished surfaces for fine-line geometries. They improve resolution and metal adhesion—essential for high-Q devices.

 

Material Highlights

• Alumina – Rugged ceramic with stable dielectric properties; ideal for cost-effective RF builds up to 30 GHz.

• Aluminum Nitride (AlN) – High thermal conductivity with solid RF performance.

• Glass – Ultra-smooth and planar; perfect for interposers, microfluidics, and 3D integration.

• Quartz – Ultra-low dielectric loss and thermal expansion; excellent beyond 100 GHz.

• Sapphire – Chemically inert, optically clear, and biocompatible; ideal for medical and RF.

• Diamond – The gold standard in thermal management and high-frequency performance.

The right substrate turns a capable design into a production-grade system.

Metallization: The Engineered Backbone of Every Thin-Film Circuit

The right stack-up defines your device’s electrical integrity, thermal performance, and reliability under bonding, reflow, or mission stress. 

Tailor every stack for:

• Adhesion strength – To anchor metals to ceramic, glass, or polymer substrates.

• Electrical performance – Low resistance, stable conduction, and controlled impedance.

• Compatibility – With bonding wires, solders, laser trimming, and passivation.

• Thermal durability – Surviving heat cycles, reflow soldering, and extended life.

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Layer-by-Layer, Purpose-Built

Adhesion Layer: (Typical Thickness: 300–800 Å) Anchors the stack to the substrate. 

Typical materials: Titanium (Ti), Chromium (Cr), Titanium-Tungsten (TiW)

Conductor Layer: Forms the main electrical paths—low resistance and high current.
Options include:

• Gold (Au): (Typical Thickness: 0.5–5.0 µm)

  • ≥1 µm Au for standard wire bonding

  • ≥2–3 µm Au when repeated bonding, probe testing, or sliding contact is expected

  • Ideal for wire bonding, corrosion resistance, low contact resistance.

• Copper (Cu): (Typical Thickness: 2–25 µm)

  • ​High-current performance with excellent thermal conductivity.

  • Thickness should match the expected current load and frequency.

  • For RF designs, consider skin depth—thicker isn’t always better.​

• Aluminum (Al): Low mass, widely used in IC-compatible designs

Resistor Layer (Optional): (Typical Values: 30–70 Ω/sq) For embedded, laser-trimmable resistive elements.
Preferred material: Tantalum Nitride (TaN) for its low TCR and long-term drift stability.

Diffusion Barrier (Optional): (Typical Thickness: 500–2000 Å)
Protects against metal migration and intermetallic formation, especially in high-temp environments.
Common barrier: Nickel (Ni)

 

Metal Stack Recommendations by Application

RF Wirebonded Builds

• Recommended Stack: TiW / Au or TaN / TiW / Au

• TiW / Au: Standard for gold wire bonding and clean signal paths

• TaN / TiW / Au: Adds integrated resistors for RF biasing or matching

• Avoid soldering with Pb/Sn—thermal cycles may cause delamination or resistor drift.

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Mixed Bonding + Soldering (Pb/Sn or SAC)

• Recommended Stack: Ti / Cu / Ni / Au

• Cu: High conductivity, cost-effective

• Ni: Protects against gold embrittlement

• Au: Ensures low-contact resistance and bondability

• Ensure proper Ni thickness (~2–5 µm) to handle temp excursions >300°C.

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Power-Handling or Cost-Sensitive Builds

• Recommended Stack: Ti / Cu

• Excellent for high current and budget-conscious applications

• Encapsulate Cu to prevent oxidation and performance loss over time.​

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Integrated Resistor Networks

• Recommended Stack: TaN included (with TiW / Ni / Au as needed)

• TaN: Laser-trimmable, stable, precision resistors

• Sheet resistance defined per design layout and geometry

• Minimize thermal exposure during reflow to preserve resistor values.

 

Soldering with Pb/Sn Alloys

• Avoid Au-only stacks—gold embrittlement is a known failure mode.

• Always include a Nickel barrier between Au and base metal to protect joints.

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Whether you're using plate-up or etch-back, your process flow affects:

• Final thickness tolerances

• Line-edge definition

• Adhesion and step coverage

Always validate your stack under real-world load—to ensure long-term performance.

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Minimum Line Width & Space

• Minimum Line and Space: 25 µm  / 25 µm. 

• This ensures consistent feature resolution, clean sidewalls, and high yield.

• Designs below this threshold may be possible, but yield and cost should be carefully evaluated.

• L/S Tolerance: ±3 µm

• Via Diameter: ≥ 50 µm

• Alignment Accuracy: ±13 µm

• Laser Tolerance: ±50 µm

Substrate Machining and Via Design

Thin-film circuits increasingly demand vertical connectivity and heat dissipation.

Functional Vias and Cavities

• Machined features for vertical interconnects, thermal management, or embedded structures

• Located either centrally or near die edges

• Can be filled with metal or left bare depending on electrical and thermal needs

Castellated Rims

• Edge-cut vias used for sidewall connectivity, module integration, or test access

Filling Options

• Electroplated Copper (Cu): Best for thermal conductivity and structural integrity

• Electroplated Gold (Au): Ideal for biocompatibility, corrosion resistance, and solderable bond pads

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Design Realities to Consider

Wall Taper: All machined vias—laser or mechanical—have natural taper. The angle depends on substrate material, thickness, and machining method.

Via Placement: Avoid locating vias too close to the die edge. Maintain clearance to reduce risk of cracking during singulation or thermal cycling.

Surface Planarity: After filling, vias are planarized for smooth topography.

• Alumina: Standard CMP processes apply

• Sapphire and hard materials: Require specialized, low-pressure CMP to avoid damage

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Filled Vias vs. Plated Through Vias

Choose based on what your application demands.

• Filled Vias (e.g., Cu): Lower parasitic effects, excellent thermal conductivity, higher fatigue resistance
  Preferred for RF, medical implants, aerospace, and mission-critical systems

• Plated Through Vias (e.g., Au): Simpler, lower-cost option for standard signal transfer or prototyping
  Suitable for less demanding environments or early-stage designs

 

Engineering Guidelines

• Via Diameter: At least 60% of the substrate thickness

• Aspect Ratio: Keep below 0.6 for fill reliability

• Pad Size: At least 2× via diameter for adhesion and plating uniformity

• Pad-to-Via Alignment Tolerance: ±15 µm

• Via Pitch: ≥3× via diameter to avoid plating artifacts and ensure clean fill

• Surface Flatness Post-Fill: ±7 µm or better

• Via-to-Edge Clearance: Keep ≥100 µm from any die edge

• Via Vents: Always include to prevent voids

• Over-Metallization: Typically Cu overplate with final Au finish

Polyimides and Specialized Structures in Thin-Film RF Designs

Engineered materials and processes for compact, high-performance systems.

Polyimide Materials: Purpose-Driven Choices

• Photosensitive Polyimide: (Typical thickness - 4 to 10 µm) Used for patterned dielectrics in RF couplers, protective encapsulation of inductors, and solder dams in mixed-assembly designs. Enables fine-line definition and vertical integration.

• Dry-Etchable Polyimide: (Typical Thickness - 7 to 13 µm) Supports flexible, multilayer circuit stacks. Common in ultrasound devices, implants, and other space-constrained medical applications. Enables precise structuring with plasma etch compatibility.

• Kapton® Film: (Typical Thickness - 12.5 to 25 µm) A proven base for flexible circuits. Known for thermal stability, mechanical toughness, and long-term biocompatibility in medical and aerospace systems.

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Multilayer Metal Structures

Precision-aligned multilayer metal stacks, separated by dielectric layers like polyimide or oxide. This enables:

• Compact circuit layouts

• Shielded interconnects

• Embedded passives

• Complex signal routing

Alignment Tolerance: ±3–5 µm between layers

 

Solder Dams

Control solder flow. Protect precision. Improve yield.

Solder dams are essential in high-frequency RF modules, dense SMT assemblies, and mixed-technology builds. They prevent unwanted solder bridging, protect bond pads, and support rework-friendly zones.

• Minimum Feature Size: ≥ 75 µm (for all dam types)

• Edge Clearance: Maintain ≥ 75 µm between dams and die or substrate edge

• Thermal Tolerance: All dam types support reflow cycles up to 300°C

• Patterned Polyimide: (Typical Thickness - 3 to 7 µm) Flexible and chemically resistant. Suitable for organic stackups, but requires wider spacing and high-temp curing.

• Oxidized Nickel (NiOx) : (Typical Thickness - 3000 to 7000 Å ) Durable barrier with good solder resistance. Blocks gold diffusion and holds up under reflow.

• Titanium-Tungsten (TiW): (Typical Thickness -  ≥ 1000 Å) Highly adhesive, tightly defined, and rugged. Ideal for RF circuits with tight geometry and limited real estate.

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Metallic dams (NiOx, TiW) provide superior edge control and thermal durability, especially valuable in dense component layouts.

• Define No-Paste Zones Clearly: Especially near bond pads, connectors, and high-frequency paths

• Use TiW for Tight Layouts: When space is limited, TiW provides crisp boundaries and long-term adhesion

• Use Ni for Balanced Builds: Offers a strong solder barrier without sacrificing pad accessibility

• Use Polyimide When Versatility Is Key: Works well on complex or flexible circuits—just allow for thermal cure and spacing

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Selective Conformal Coating

Targeted protection without compromising access.
Our selective conformal coating process guards critical circuit areas from moisture, dust, and contaminants—while leaving connectors and test points fully accessible.

Design Guidelines:

• Clearly define no-coat zones in your layout for reworkable components

• Standard coating thickness: 25–125 µm, optimized for environmental exposure and clearance requirements​